The present invention is related to the design of FPGA (Field Programmable Gate Array) core cell designs and, in particular, to core cells based upon LUTs (Look-Up Tables).
FPGAs are integrated circuits whose functions are defined by the users of the FPGA. With shrinking geometries in semiconductor technology, FPGA cores, the main portion of FPGAs after the peripheral circuits have been removed, are also embedded with other defined elements or circuit blocks in ASICs (Application Specific Integrated Circuits). The user programs the FPGA or FPGA core (hence the term, “field programmable”) to perform the functions desired by the user. (Henceforth, the term, FPGA, is used to include both the discrete FPGA device and the FPGA core unless a distinction is specifically made.) The FPGAs have an interconnection network between the logic cells or blocks, and the interconnection network and the logic cells are configurable to perform the application desired by the user. For FPGAs based on SRAM (Static Random Access Memory) cells to hold the configuration bits, the configuration of the FPGA can be repeatedly changed by the user for multiple applications of the electronic system. For FPGAs based on manufacturing mask programming (for example, a via mask), the configuration of the FPGA is performed only once.
In most cases, the logic cells of an FPGA are implemented in the form of a look-up table, rather than an assemblage of programmable logic gates. A look-up table (LUT) with x number of inputs can implement any Boolean logic function of x variables and there are algorithms which can map a given Boolean logic network into a network of LUTs with a minimum delay through the network.
The present invention is directed toward improving the packing of the LUT-based FPGA logic cells so that the FPGA occupies less space for the same degree of functionality. The resulting manufacturing yields of the integrated circuit, either FPGA or ASIC, is increased and costs are lowered. In addition, reducing the number of LUTs required for a given functionality generally increases the speed of the implemented function.